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Pyjong10935yWhat is TPM? Also, afaik A20 does not reset anything, it enables the address bus from bit 20 higher. Also I think the support of the primary bus type highly depends on the particular processor's root complex. I may be wrong here but I'd be really surprised if ISA was an option on any of the new cpus as in "to reprogramm all pins and root complex to do ISA". Also, what are you upset about? Whats the rant?
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Pyjong10935yYeah I checked against the PCIe 3.0 spec and the mindshare book and the ISA enable bit in bridge control register is not part of the PCIe spec. It may have been on conventional PCI. Are you sure this still works?
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Parzi88335y@Pyjong didn't say the PCI bus controlled ISA, merely the processor supports it. It'd be easier to use a PCI-e daughterboard than to literally add your own slot from scratch.
And I don't have to be upset about anything to rant about interesting tech shit...
on the A20 line thing,
"""
These behaviors have been used by plenty of software that expects this behavior, and therefore keyboard controllers have continued controlling the A20 line and performing software CPU resets even when the need for a reset via the keyboard controller was obviated by the Intel 80386's ability to switch to real mode from protected mode without a CPU reset. The keyboard controller also handles PS/2 mouse input if a PS/2 mouse port is present. Today the keyboard controller is either a unit inside a Super I/O device or is missing, having its keyboard and mouse functions handled by a USB controller and its role in controlling the A20 line handled by the chipset.
""" - Wikipedia -
Pyjong10935y@Parzi Yes that is what I'm questioning. The CPUs don't support that anymore as the root complex is PCI express.
Have you read the thing you posted? That doesn't mean you set A20 and it resets the CPU. It says if you need to reset A20 (clear or set to zero) you no longer have to reset the CPU. Man I have actually done this in assembly, can you take my word on this? Please take the easy way out of this and say your memory slipped.. -
Parzi88335y@Pyjong "please take the easy way out on this"
the fucking linux kernel uses the keyboard controller as a fallback to reboot if ACPI fails (and then triple faults the CPU if both fail, but, y'know)
also the LPC bus is basically the ISA bus but with fewer pins. -
Pyjong10935y@Parzi I think you are right with ISA thing. Xeon d-1500 seems to have some support, according to the datasheet. I stand corrected.
With the A20 however, I think you are making stuff up. Can you please link to the line of code that resets the cpu on Bootlin? I don't believe you, as it seemed you just misinterpreted text on Wikipedia. I have also used A20 myself and it served something completely else. That being said if there is some trick in the source and you post the link to it, I will apologize. -
Parzi88335yhttps://github.com/torvalds/linux/...
Fairly sure this is it.
Addendum: """
The LPC bus has replaced the ISA bus as the connection to the legacy I/O devices on recent motherboards; while physically quite different, LPC looks just like ISA to software, so that the peculiarities of ISA such as the 16 MiB DMA limit (which corresponds to the full address space of the Intel 80286 CPU used in the original IBM AT) are likely to stick around for a while.
"""
https://nixsys.com/isa-bus-current-... -
Pyjong10935y@Parzi Ah I see. Yeah, as the text you posted said: "it is no longer required to reset cpu for clearing A20".
Now this code you pointed to, clears A20, because after reboot it's supposed to be cleared and then switches to different reboot method. Programming the keyboard controller does not do the CPU reset itself.
TIL all x86-compatible CPUs have ISA support and the ability to be reset by the keyboard controller via A20 line, all thanks to not wanting to alienate a single person who refuses to upgrade.
you can put ISA or AGP devices straight onto the fucking LPC bus and it'll work on most CPUs. Y'know, on the same bus as the TPM in most?
you already know i'm gonna put a floppy controller, a parallel port, and an IDE controller on the PCI-e bus with an ISA daughterboard
rant