Going through code of a bluespec verilog core
This language is some jungle shit !!
is there any intuitive HDL exists or it’s just a myth

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    Hey hey, Bluespec is beautiful once you get used to it (apart from timing, timing is a bitch and a mess of RWires and stuff)

    I agree that Bluespec Systemverilog is shit to look at and probably not the cleanest way of expressing Bluespec's ideas (that would be the original implementation, Bluespec Haskell, but nobody outside academia understood it so they had to compromise and make BSV).
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    @RememberMe it’s talking toll on my fragile brain
    I think documents are not good enough
    I clearly don’t understand why make bluespec language on top of verilog
    What deficiency in verilog they are trying to address
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    @hardfault http://csg.csail.mit.edu/6.375/...

    http://csg.csail.mit.edu/6.375/... (this is the practical one).

    It basically introduces higher abstractions and a solid type system for handling complex designs. Verilog works at the level of connections and wires, it describes structure very well but not behaviour. Bluespec describes behaviour very well but is iffy on low level structural control. We just use both when appropriate.
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