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Search - "verilog"
GOD DAMN IT COLLEGE YOU DID IT AGAIN. for real college can go suck Satan's 50 inch red cock for all I care.
A professor asked me to design a processor and I'll get a bonus. I said okay cool nothing hard.
oh but it has to be in verilog.
oh and it has to be on this fucking ancient useless piece of shit called xilinx that the fucking college provides to you only via a fucking 50 gigabyte virtual machine.
sigh. okay..... challenge accepted.
It fucking crashes every 2 minuites. And after 3 days of no sleep. I finally finished the Alu, Control unit, 4k memory, 8 registers and the busses.......... BUT THEN THE ENTIRE VIRTUAL MACHINE CRASHED AND LOST ALL PROGRESS...... fml.
and the professor only gave me the bonus for the Alu. sigh. fuck college.12
I just saw that ARM released their design start IP for Cortex M0 for free to the masses , it’s obfuscated verilog code.
I worked on SoC design based on this in college but it took a lot of paper work to get these file but now they are free to download
This is exciting as this makes a open-source community based microcontroller design possible.
Only missing piece here is the verilog compiler they use is not open source .
Has anyone messed around with Cortex M0 DS + ghdl or iverilog. I am about to start a little side project will update more on this25
An OSS library made me learn a new language and I am so happy it did!
I came across a well implemented System Verilog parser written in Rust. It was so good to see someone putting in the effort to write that library, I wanted to contribute to it. I had zero knowledge in Rust but I thought, what the heck, let me learn it.
And man it was a steep learning curve. After a 2 weeks or so, now I have very basic understanding of the language. What better way to learn something than just diving into an actual project?
So, today I raised an issue to the developer for a possible improvement to the library. I hope he accepts it
on an interview the interviewer said that there's a question on the test that seems simple but actually has a more sophisticated solution. and all i thought of and wrote was a simple solution. hmm1
Currently I have to devop a Verilog Module. Somehow there seems to be a bug in my environment and once I start the compile process this fucking compiler hangs for a solid 30 minutes or longer and I don't even get an output. It just stops with an Error that says I shall check the logfile, but it is empty.1