HDL choices:
Verilog: Spend hours finding bugs in implicit type casts.
VHDL: Spend hours writing type casts.

SystemVerilog: spend hours figuring out why Cadence tools think something is a-ok but Synopsys tools don't

Chisel: actually a nice experience

Stratus/Vivado HLS: haha for-loop go brrrr

Vitis/OpenCL: spend hours on why all your memory accesses are happening serially

Bluespec: what is "time"?