23
FuckJava
123d

Reading this in a routine:

NOP
NOP
NOP
RET

Comments
  • 0
    Huh... you sure it wasn't the other way around?
  • 0
  • 1
    @FuckJava huh, so what's the idea?
  • 6
    @Pyjong
    Wasting three CPU clock cycles before returning, so the whole routine would take a fixed number of cycles. I read this on an AMI BIOS chip
  • 1
    @FuckJava Humm, ok. That's weird.
  • 1
    @Pyjong
    Is it? I've don't it a couple of times myself on AVR for timing reasons
  • 0
    @FuckJava Emm, so did you read it in the source or did you download your bios flash?
  • 2
    @Pyjong
    I was using debug.com, and was reading the interrupt handler for INT19h when I came across it for the first time. It was over 20 years ago...
  • 0
    @FuckJava Heheh debug.com, that's pretty old school :)
  • 1
    @Pyjong
    That's me
  • 0
  • 1
    @irene
    I wouldn't have a clue... I was young back then and can't remember much
  • 2
    Isn't that even normal today? For example waiting for data from ram would do something similar.

    You can get pretty creative, especially when multiple things run at the same time. A friend did wonders with that in the Game TIS-100 (really fun, you should try it), while I usually kept it synchronized by waiting for data.
  • 6
    Some years ago when heroes of the storm were in closed beta, I lost my access before release, so I chcked the binary cuz maybe there are some bytes worth noping out. And close to beginning of the exe I found a tight loop that counted from 64k down to zero. Which is also pretty weird. I asked about it on osdev without giving a context and one guy replied in the way: yeah we used that in old games for the hardware to get ready xD . Maybe blizzard never removes old code.. I mean storm.dll was created fairly long time ago.
  • 1
    might be required for hardware sync, due to bein in a BIOS and all? Burning cycles is a common practice for that situation, so...
  • 1
    @LinusCDE
    CPU can wait for 100 of cycles before the ram gets you the data.
    Yup ram is slow. That is why cache exists.
  • 7
    @FuckJava For the young folks out there debug.com is a command line tool built into DOS and not a domain name. :)
  • 2
    Obviously, I would shorten the nop-nop-nop-ret to ret, but that's my special skill. ^^

    When you set some IO pin, it may take some moments before the change arrives. Remember that lines on the board have a capacitance and don't change their level instantaneously. Waiting until a proper steady signal level has been reached isn't uncommon.

    Another thing is that some CPUs have instructions that don't have their effect right after the program counter has gone past them, but some clocks later.
  • 1
    @FuckJava Not exactly 3 ticks, but some 3*n ticks. Each instruction fetch, decode, execute can take multiple cycles in the pipeline.
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