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Cool tool, will check out.
In the full adder, isn't the carry out the OR of the carry outs of the half adders? (You've done XOR)
Also, this architecture works functionally (after you fix the full adder) but has a very fundamental flaw when it comes to practical use. Can you see it?
@RememberMe went by the xor-based half-adder under the 'adder_(electronics)' article on wikipedia. Looking at the diagrams, damn, you're right! It should have been an OR not a XOR.
In terms of flaws, the only problems I can see are 1. it doesnt allow overflow, 2. doesnt allow for negative numbers, 3. it has too many inputs? (well that last one is a guess).
Also the pins could use labeling but I don't think that works in the program yet.
The nice thing about it is that each circuit can be reused as individual chips in circuits at higher levels, which is cool modularity-wise.
Still haven't seen a program like it that 1. lets you add LEDs to a chip, and then represents those as individual pixels on a screen at a higher level though.
Nor anything that lets you represent ROM or writeable disks or tape.
Shenzhen/io was one that came closest, but thats more of a toy/game than a proper simulator.
Also, the full adder should have an input pin and an output pin on the first and last carry so I can chain it with other adders?
@Wisecrack yes, no support for overflow detection is a problem, but not crucial. This logic with some minor modifications will actually work just fine with negative integers, look up 2's complement arithmetic.
The real problem here, and why this design (called a ripple carry adder) is not used in hardware is the long critical path.
Circuits take some time to respond to changes in input because nothing moves infinitely fast ("processing delay"). Look at the 8bit adder. The first full adder (FA) takes some time, call it T seconds, to respond to its inputs, and produces a sum and carry signal. You can't use its outputs between 0 to T seconds (the outputs are invalid from 0 to T seconds), because the FA hasn't finished responding to the inputs yet.
From the POV of the second FA, one of the *inputs* is invalid from 0 to T seconds (because it's an output of the first FA). When the input stabilizes at T seconds, the second FA takes a further T seconds to finish its computation, so its sum and carry outputs are only valid after 2T seconds. From 0 to 2T seconds, the second FA's outputs are invalid (from 0 to T it has an invalid input, and from T to 2T it's "calculating" its outputs).
Similarly, the third FA's outputs are valid only after 3T seconds, the fourth's outputs after 4T seconds...the nth FA's output is valid only after nT seconds, which is linear in number of bits and multiplied by the full delay of a FA. That's really, really long, making this a slow design.
The problem is that long linear chain of carries (hence "ripple carry") which makes each FA dependent on the entire previous FA. The longest chain of delays is called the critical path, because it determines how fast your circuit can produce a valid output. Faster adders can use eg. carry lookahead/carry save/ etc. to mitigate this.
I know you've just started, but this is a common pitfall to fall into for HW, many beginners get confused why their circuits are so slow.
Looks good :)
Logisim is a tool that has also all the functionality you wish. I use it to check my circuit synthesis for uni. Its very helpfull. I wish you good luck with your following operations.